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ltc2926 1 2926fa 15.0k 9.53k 0.1 f 2926 ta01 ltc2926 ramp fb2 out sense rampbuf track1 track2 pgtmr gnd v cc v cc d1 15.0k 4.02k fault 10k 1 f sgate1 10 ? sgate2 10 ? 100 ? v cc status irf7413z irf7413z on 10k 1.8v module 1.8v slave1 out sense d2 100 ? 3.3v module 3.3v slave2 s2 15.0k 4.02k status/pgi fb1 s1 15.0k 9.53k fault on/off 0.1 f mgate mosfet-controlled power supply tracker the ltc2926 provides a simple solution for tracking and sequencing up to three power supply rails. an n-channel mosfet and a few resistors per channel con? gure the load voltages to ramp up and down together, with voltage offsets, with time delays or with different ramp rates. automatic remote sense switching compensates for voltage drops across the mosfets. the ltc2926 provides two integrated switches as well as a signal to control optional additional external n-channel mosfet sense switches. the ltc2926 includes i/o signals for communication with other devices. the status output asserts after tracking and sequencing have completed. a low voltage on the power good input after an adjustable timeout period causes load disconnect. a low voltage on the fault i/o causes immedi- ate load disconnect. until it is reset, a fault latch prevents tracking and keeps the loads disconnected. v core and v i/o supply tracking microprocessor, dsp and fpga supplies servers communications systems flexible power supply tracking and sequencing adjustable ramp rates, offsets and time delays controls three supplies with series mosfets integrated remote sense switching fault input/output status output/power good input available in 20-lead narrow ssop and 20-lead qfn (4mm 5mm) packages applicatio s u features typical applicatio u descriptio u , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *protected by u.s. patents including 6897717. 2926 ta01b 500mv/div 3.3v slave2 1.8v slave1 5ms/div 2926 ta01c 500mv/div 3.3v slave2 1.8v slave1 5ms/div
ltc2926 2 2926fa supply voltage (v cc ) ................................. C0.3v to 10v input voltages on ......................................................... C0.3v to 10v ramp .............................................C0.3v to v cc + 1v track1, track2 ........................C0.3v to v cc + 0.3v pgtmr ........................................C0.3v to v cc + 0.3v input/output voltages fault .................................................... C0.3v to 10v status/pgi (note 3) .......................... C0.3v to 11.5v output voltages rampbuf ....................................C0.3v to v cc + 0.3v fb1, fb2, d1, s1, d2, s2 ....................... C0.3v to 10v mgate, rsgate (note 3) ................... C0.3v to 11.5v sgate1, sgate2 (note 3) .................. C0.3v to 11.5v (notes 1, 2) rms currents track1, track2 ................................................5ma fb1, fb2 ..............................................................5ma d1, s1, d2, s2 ...................................................30ma operating temperature ltc2926c ................................................ 0c to 70c ltc2926i ............................................. C40c to 85c storage temperature range gn package ....................................... C65c to 150c ufd package ...................................... C65c to 125c lead temperature (soldering, 10 sec) gn package ...................................................... 300c absolute axi u rati gs w ww u package/order i for atio uu w gn package 20-lead plastic ssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 v cc track1 fb1 s1 sgate1 d1 on pgtmr fault gnd rampbuf track2 fb2 s2 sgate2 d2 status/pgi rsgate mgate ramp t jmax = 125c, ja = 85c/w 20 19 18 17 7 8 top view ufd package 20-lead (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 21 13 14 15 16 fb1 s1 sgate1 d1 on pgtmr fb2 s2 sgate2 d2 status/pgi rsgate track1 v cc rampbuf track2 fault gnd ramp mgate exposed pad (pin 21) is gnd pcb connection optional t jmax = 125c, ja = 43c/w order part number order part number ufd part marking* ltc2926cgn ltc2926ign ltc2926cufd LTC2926IUFD 2926 2926 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges.*the temperature grade is identi? ed by a label on the shipping container.
ltc2926 3 2926fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 3.3v unless otherwise speci? ed. symbol parameter conditions min typ max units supply voltage v cc input supply voltage operating range 2.9 3.3 5.5 v i cc input supply current i trackn = 0ma, i fbn = 0ma, i rampbuf = 0ma 1.5 2.5 3.5 ma i trackn = C1ma, i fbn = C1ma, i rampbuf = C3ma 8.5 9.5 10.5 ma v cc(uvlo) input supply undervoltage lockout v cc rising 2.2 2.4 2.6 v v cc(uvlo) input supply undervoltage lockout hysteresis 15 50 75 mv control and i/o v on(th) on pin threshold voltage v on rising 1.20 1.23 1.26 v v on(th) on pin threshold voltage hysteresis 40 75 110 mv i on on pin input current v on = 1.2v, v cc = 5.5v 0 100 na v on(clr) on pin fault clear threshold voltage v on falling 0.465 0.500 0.535 v t clr fault clear delay v on falling 1 3 10 s v on(arm) on pin fault arm threshold voltage v on rising 0.565 0.600 0.635 v t arm fault arm delay v on rising 1 4.5 10 s v fault(th) fault pin input threshold voltage v fault falling 0.465 0.500 0.535 v i fault(up) fault pin pull-up current fault latch clear, v fault = 1.5v C3.0 C8.5 C13 a v fault(ol) fault pin output low voltage fault latch set, i fault = 5ma, v cc = 2.7v 100 400 mv v fault(oh) fault pin output high voltage (v cc C v fault ) fault latch clear, i fault = C1a 300 550 900 mv v pgi(th) status/pgi pin input threshold voltage v status/pgi rising 1.10 1.23 1.36 v v pgi(th) status/pgi pin input threshold voltage hysteresis 30 75 150 mv i pgi(up) status/pgi pin pull-up current status/pgi on, v status/pgi = 1.5v C7 C10 C13 a v status(ol) status/pgi pin output low voltage v on low, i status/pgi = 5ma, v cc = 2.7v 200 400 mv v status(oh) status/pgi pin output high voltage (v status/pgi C v cc ) i status/pgi = C1a 5.0 5.5 6.0 v v pgtmr(th) pgtmr pin threshold voltage v pgtmr rising 1.10 1.23 1.36 v i pgtmr(up) pgtmr pin pull-up current on high, v pgtmr = 1v C8 C10 C12 a i pgtmr(dn) pgtmr pin pull-down current on low, v pgtmr = 0.1v, v cc = 2.7v 0.5 4 10 ma v pgtmr(clr) pgtmr pin clear threshold voltage v pgtmr falling 50 100 150 mv ramp buffer i ramp(in) ramp pin input current 0v < v ramp < 5.5v, v cc = 5.5v 01 a v rampbuf(os) ramp buffer offset voltage v ramp = 1/2 v cc , i rampbuf = 0ma 0 10 mv v rampbuf(ol) rampbuf pin output low voltage i rampbuf = 3ma 32 60 mv electrical characteristics
ltc2926 4 2926fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 3.3v unless otherwise speci? ed. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into the device pins are positive; all currents out of the device pins are negative. all voltages are referenced to ground unless otherwise speci? ed. symbol parameter conditions min typ max units v rampbuf(oh) rampbuf pin output high voltage (v cc C v rampbuf ) i rampbuf = C3ma 60 80 mv tracking channels i error(%) i fbn to i trackn current mismatch (i fbn C i trackn )/i trackn ? 100% i trackn = C10a i trackn = C1ma 0 0 3 3 % % v track track pins voltage i trackn = C10a i trackn = C1ma 0.776 0.776 0.800 0.800 0.824 0.824 v v v fb(ref) fb pins internal reference voltage v trackn = v cc , i fbn = 0ma 0.784 0.800 0.816 v i fb(leak) fb pins leakage current v fbn = 0.8v, v cc = 5.5v 0 10 na v fb(clamp) fb pins clamp voltage C1ma < i fbn < C1a 1.7 2.0 2.4 v master ramp and supply v mgate mgate pin external n-channel gate drive (v mgate C v cc ) i mgate = C1a 5.0 5.5 6.0 v i mgate(up) mgate pin pull-up current fault latch clear, v on high, v mgate = 3.3v C7 C10 C13 a i mgate(dn) mgate pin pull-down current fault latch clear, v on low, v mgate = 3.3v 71013 a i mgate(fault) mgate pin fault pull-down current fault latch set, v on high, v mgate = 5.5v, v cc = 5.5v 52050 ma slave supplies v sgate sgate pins external n-channel gate drive (v sgaten C v cc ) i sgaten = C1a, v fbn = 0.75v 5.0 5.5 6.0 v i sgate(up) sgate pins pull-up current fault latch clear, v fbn = v fb(ref) C 10mv, v sgaten = 3.3v C6 C10 C13 a i sgate(dn) sgate pins pull-down current fault latch clear, v fbn = v fb(ref) + 10mv, v sgaten = 3.3v 61013 a i sgate(upfst) sgate pins fast pull-up current fault latch clear, v fbn = 0v, v sgaten = 3.3v C21 C30 C39 a i sgate(dnfst) sgate pins fast pull-down current fault latch clear, v fbn = 1v, v sgaten = 3.3v 21 30 39 a i sgate(fault) sgate pins fault pull-down current fault latch set, v on high, v sgaten = 5.5v, v cc = 5.5v 52050 ma remote sense switches v rsgate rsgate pin external n-channel gate drive (v rsgate C v cc ) i rsgate = C1a 5.0 5.5 6.0 v i rsgate(up) rsgate pin pull-up current fault latch clear, switches on, v rsgate = 0v C7 C10 C13 a i rsgate(dn) rsgate pin pull-down current fault latch clear, switches off, v rsgate = 3.3v 71013 a i rsgate(fault) rsgate pin fault pull-down current fault latch set, switches off, v rsgate = 5.5v, v cc = 5.5v 52050 ma v rsgate(th) rsgate pin threshold voltage ramping completed on pin low, rsgate falling 1.10 1.23 1.36 v r sw(on) remote sense switch on-resistance switches on, v dn = v cc + 0.3v, i sn = C10ma 210 note 3: the mgate, sgate1, sgate2, rsgate and status/pgi pins are internally limited to a minimum of 11.5v. driving these pins to voltages beyond the clamp level may damage the part. electrical characteristics
ltc2926 5 2926fa temperature ( c) i mgate(pd) , i rsgate(pd) (ma) 2926 g08 v cc = 5.5v v cc = 3.3v v cc = 2.9v C50 25 75 C25 0 50 100 30 25 20 15 10 0 5 mgate, rsgate pins fault latch set v cc (v) 2.5 i gate(pd) (ma) 6.0 2926 g07 3.0 3.5 4.0 4.5 5.0 5.5 30 25 20 15 10 0 5 fault latch set mgate, rsgate, sgate1, sgate2 pins i load ( a) gate drive (v) 6 0 5 4 3 2 1 2926 g06 01525 510 20 35 30 mgate, rsgate, sgate1, sgate2 pins pull-up mode sgate1, sgate2 pins fast pull-up mode gate drive = v pin C v cc v cc (v) 2.5 gate drive (v) 6.0 2926 g05 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.8 5.6 5.4 5.2 5.0 gate drive = v pin C v cc mgate, rsgate, sgate1, sgate2 pins i gate = C1 a v cc (v) 2.5 i cc (ma) 12 10 8 6 4 2 0 4.0 5.0 2926 g01 3.0 3.5 4.5 5.5 6.0 i rampbuf = C3ma i trackn = C1ma i fbn = C1ma i rampbuf = 0ma i trackn = 0ma i fbn = 0ma temperature ( c) i cc (ma) 12 10 8 6 4 2 0 2926 g02 i rampbuf = C3ma i trackn = C1ma i fbn = C1ma i rampbuf = 0ma i trackn = 0ma i fbn = 0ma C50 25 75 C25 0 50 100 temperature ( c) v track (v) 0.812 0.808 0.804 0.800 0.796 0.792 0.788 2926 g03 i track = C10 a i track = C1ma C50 25 75 C25 0 50 100 supply current vs supply voltage supply current vs temperature track pin voltage vs temperature gate drive voltages vs supply voltage gate drive voltages vs load current mgate, rsgate fault pull-down currents vs temperature sgate fault pull-down current vs temperature typical perfor a ce characteristics uw gate fault pull-down currents vs supply voltage temperature ( c) i sgate(pd) (ma) 2926 g09 v cc = 5.5v v cc = 3.3v v cc = 2.9v C50 25 75 C25 0 50 100 30 25 20 15 10 0 5 sgate1, sgate2 pins fault latch set speci? cations are at t a = 25c, v cc = 3.3v unless otherwise speci? ed.
ltc2926 6 2926fa v cc (v) 2.5 v ol (mv) 6.0 2926 g12 3.0 3.5 4.0 4.5 5.0 5.5 250 200 150 100 50 0 status/pgi pin fault pin i status/pgi = 5ma i fault = 5ma rampbuf output high voltage vs temperature logic output low voltages vs supply voltage typical perfor a ce characteristics uw rampbuf output low voltage vs temperature temperature ( c) v ol (mv) 2926 g10 v cc = 5.5v v cc = 2.9v C50 25 75 C25 0 50 100 50 30 40 20 10 0 i rampbuf = 3ma temperature ( c) v oh (mv) 2926 g11 v cc = 5.5v v cc = 2.9v C50 25 75 C25 0 50 100 100 60 80 40 20 0 i rampbuf = C3ma v oh = v cc C v rampbuf speci? cations are at t a = 25c, v cc = 3.3v unless otherwise speci? ed.
ltc2926 7 2926fa d1, s1, d2, s2 (pins 6, 4, 15, 17/pins 4, 2, 13, 15): remote sense switches #1 and #2. a 10 (max) switch connects each pair of pins (d1/s1 and d2/s2) after mgate, sgate1 and sgate2 are all fully enhanced (mgate > ramp + 4.9v or ramp > v cc , and sgate1, sgate2 > v cc + 4.9v). the switch can be used to compensate for the voltage drop across the external mosfet that controls a slave or the master supply. connect the switch between the load and the supplys sense node. before the external mosfet is fully enhanced, a resistor between the supplys output and sense nodes provides local feedback. when the on pin voltage is low, the switch will open before the mgate, sgate1 and sgate2 pins will ramp down. leave unused switch terminal pairs unconnected. exposed pad (pin 21, ufd package only): exposed pad may be left open or connected to device gnd. fault (pin 9/pin 7): negative-logic fault input/output. under normal conditions the internal fault latch is not set and an 8.5a current pulls up fault to a diode drop below v cc . when the voltage at fault is pulled below 0.5v, a fault condition is latched and an internal n-channel mos- fet pulls fault to gnd until the latch is reset. the fault condition also pulls status/pgi low, opens the remote sense switches, and pulls mgate, sgate1 and sgate2 to gnd to disconnect the master and slave supplies from their loads. pulling status/pgi below 1v after the power good time-out delay also latches a fault. the fault latch is reset when the on pin voltage is below 0.5v, or when v cc is undervoltage. the fault latch is armed when the on pin voltage exceeds 0.6v. to auto-retry after a fault, connect fault to the on pin. leave the fault pin unconnected if it is unused. fb1, fb2 (pins 3, 18/pins 1, 16): feedback control in- put/outputs. each fb pin connects to the feedback node of a slave supply. connect an fb pin to the tap point of a resistive voltage divider between the source (load side) of the external mosfet and gnd. for a slave supply with an accessible feedback path, no external mosfet may be necessary. in that case, connect an fb pin to the tap point of a resistive voltage divider between the supply generators feedback node and gnd. to prevent damage to the slave supply, the fb pins will not force the slaves feedback node above 2.4v. in addition, it will not actively sink current even when the ltc2926 is not powered. tie unused fb pins to gnd. gnd (pin 10/pin 8): device ground. mgate (pin 12/pin 10): master gate drive for external n-channel mosfet/master ramp. when the on pin is high, an internal 10a current charges the gate of an external n-channel mosfet. a capacitor from mgate to gnd sets the master ramp rate. add a 10 resistor between the capacitor and the mosfets gate to prevent high frequency oscillations. an internal charge pump guarantees that the mgate pin voltage will pull up to 5.5v above v cc , which ensures that logic-level n-channel mosfets are fully enhanced. when the on pin is pulled low, the mgate pin is pulled to gnd by a 10a current source. upon a fault condition, the mgate pin is pulled low immediately with 20ma. to create a master ramp signal without an external mosfet, tie the mgate pin to the ramp pin. a weak internal clamp on the ramp pin limits mgate to v cc + 1v in this case. leave the mgate pin unconnected if it is unused. on (pin 7/pin 5): on control input. the on pin has a threshold of 1.23v with 75mv of hysteresis. a high causes 10a to ? ow out of the mgate pin, ramping up the supplies. a low causes 10a to ? ow into the mgate pin, ramping down the supplies. pull the on pin below 0.5v to reset the fault latch. pull the on pin above 0.6v after a fault latch reset to arm the fault latch. pgtmr (pin 8/pin 6): power good timer. connect an external capacitor between pgtmr and gnd to set the power good time-out delay. when the on pin is above 1.23v, a 10a current pulls up pgtmr to v cc , otherwise an internal n-channel mosfet pulls pgtmr to gnd. if the voltage on pgtmr exceeds 1.23v and the voltage on status/pgi is not above 1.23v, a fault condition is latched, the remote sense switches are opened, and fault, status/pgi, mgate, sgate1, sgate2 and rsgate will be immediately pulled to gnd. to disable the power good timer tie pgtmr to gnd. gn/ufd packages pi fu ctio s uuu
ltc2926 8 2926fa ramp (pin 11/ pin 9): ramp buffer input. connect the ramp pin to the master ramp signal to force the slave supplies to track it. when the ramp pin is connected to the source of an external n-channel mosfet, the slave supplies track the mosfets source, the master supply voltage, as it ramps up and down. when a master supply is not required, the ramp pin can be tied directly to the mgate pin to form a master ramp voltage. in this con? gura- tion, the supplies track the capacitor on the mgate pin as it is charged and discharged by the 10a current source that is controlled by the on pin. the ramp pin is weakly clamped to v cc + 1v. do not drive ramp above v cc with a low impedance source to avoid sinking large currents into the pin. ground the ramp pin if it is unused. rampbuf (pin 20/pin 18): ramp buffer output. the rampbuf pin provides a low impedance buffered ver- sion of the signal on the ramp pin. this buffered output drives the resistive voltage dividers that connect to the track pins. limit the capacitance at the rampbuf pin to less than 100pf. rsgate (pin 13/pin 11): gate drive for internal and external n-channel mosfet remote sense switches. a remote sense path between a load and the sense input of its supply generator automatically compensates for voltage drops across the tracking mosfet. after the series mos- fets are fully enhanced, a 10a current pulls up rsgate. an internal charge pump guarantees that rsgate will pull up to 5.5v above v cc , which ensures that logic-level n-channel mosfets are fully enhanced. when the voltage at rsgate exceeds v cc + 4.9v, the status/pgi pull-down is released. when the on pin is low, a 10a current source pulls rsgate to gnd. supplies will not track down until the rsgate pin voltage falls below 1.23v, which ensures that the remote sense switches open before the loads are disconnected. connect rsgate to the gates of additional external n-channel mosfets to create more remote sense switches. upon a fault condition, the rsgate pin is pulled low immediately with 20ma. optionally connect a capaci- tor between rsgate and gnd to set the switch-on rate or to add delay between switch closure and status/pgi assertion. leave rsgate unconnected if it is unused. sgate1, sgate2 (pins 5, 16/pins 3, 14): slave gate con- trollers for external n-channel mosfets. each sgate pin ramps a slave supply by controlling the gate of an external n-channel mosfet so that its source terminal follows the tracking pro? le set by external resistors and the master ramp. it is a good practice to add a 10 resistor between this pin and the mosfets gate to prevent high frequency oscillations. an internal charge pump guarantees that the sgate pin voltage will pull up to 5.5v above v cc , which ensures that logic-level n-channel mosfets are fully enhanced. leave unused sgate pins unconnected. status/pgi (pin 14/pin 12): status output/power good input. a 10a current pulls up status/pgi when mgate, sgate1 and sgate2 are fully enhanced, and the remote sense switches are closed, otherwise an internal n-channel mosfet pulls down status/pgi. if the status/pgi pin is pulled below 1v after the power-good time-out delay (see pgtmr pin description), the fault latch is set, and mgate, sgate1, sgate2 and rsgate are all pulled low immediately. an internal charge pump guarantees that the status/pgi pin voltage will pull up to 5.5v above v cc . an external pull-up resistor may be added to limit the status/pgi voltage to logic levels. leave the status/pgi pin unconnected if it is unused. track1, track2 (pins 2, 19/pins 20, 17): tracking con- trol inputs. a resistive voltage divider between rampbuf and each track pin determines the tracking pro? le of each supply channel. each track pin pulls up to 0.8v, and the current supplied at track is mirrored at fb. the track pins are capable of supplying at least 1ma when v cc = 2.9v. they may be capable of supplying up to 10ma when the supply is at 5.5v, so care should be taken not to short this pin for extended periods. limit the capacitance at the track pins to less than 25pf. leave unused track pins unconnected. v cc (pin 1/pin 19): positive voltage supply. operating range is from 2.9v to 5.5v. an undervoltage lockout resets the part when the supply is below 2.4v. v cc should be bypassed to gnd with a 0.1f capacitor. gn/ufd packages pi fu ctio s uuu
ltc2926 9 2926fa fu ctio al block diagra uu w uvlo r sq fault latch 0.8v v cc 2926 bd fb1 rampbuf v cc track2 track1 gnd v cc 2.4v d2 fb2 s2 ramp 0.8v 1.23v v cc + 4.9v rsgate v cc 1x d1 s1 10 a 10 a 10 a/30 a 10 a/30 a uvlo pgtmr high pgi low charge pump mgate gate up charge pump 10 a C + C + 1.23v rsgate C + ramp + 4.9v mgate C + v cc ramp C + v cc + 4.9v sgate1 C + v cc + 4.9v sgate2 C + C + on C + C + C + sgate2 status/pgi fast pull-down 1.23v fault uvlo 1.23v C + 0.6v C + delay 0.5v C + delay v cc 8.5 a 0.5v C + fault r sq clear/arm signal latch v cc 10 a 0.1v C + pgtmr fast pull-down 10 a 10 a charge pump rsgate rsgate up fast pull-down charge pump sgate1 up/down fast pull-down clr/arm
ltc2926 10 2926fa power supply tracking and sequencing the ltc2926 handles a variety of power-up pro? les to satisfy the requirements of digital logic circuits including fpgas, plds, dsps and microprocessors. these require- ments fall into one of the four general categories illustrated in figures 1 to 4. some applications require that the potential difference between two power supplies must never exceed a speci- ? ed voltage. this requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply ic. typically, this is achieved by ramping the supplies up and down together (figure 1). in other applications it is desirable to have the supplies ramp up and down ratio- metrically (figure 2) or with ? xed voltage offsets between them (figure 3). certain applications require one supply to come up after another. for example, a system clock may need to start before a block of logic. in this case, the supplies are se- quenced as in figure 4, where the 1.8v supply ramps up completely followed by the 2.5v supply. operation the ltc2926 provides a simple solution to allow all of the power supply tracking and sequencing pro? les shown in figures 1 to 4. a single ltc2926 controls up to three supplies: two slave supplies that track a master signal. with just four resistors and an external n-channel mosfet, each slave supply is con? gured to ramp up and down as a function of the master signal. this master signal can be a third supply that is ramped up through an external mosfet, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the mgate and ramp pins together to an external capacitor. tracking cell and gate controller cell the ltc2926s operation is based on the combination of a tracking cell and a gate controller cell that is shown in figure 5. the tracking cell servos the track pin at 0.8v, and the current supplied by the track pin is mirrored at the fb pin. the gate controller cell servos the fb pin at 0.8v by driving the gate of the external n-channel mosfet (q ext ), and establishes the slave output voltage at the source of the mosfet based on the track pin current and resistors figure 4. supply sequencing figure 3. offset tracking figure 2. ratiometric tracking figure 1. coincident tracking applicatio s i for atio wu u u 2926 f01 500mv/div master slave2 slave1 5ms/div 2926 f02 500mv/div slave2 slave1 5ms/div 2926 f04 500mv/div slave2 slave1 5ms/div 2926 f03 500mv/div master slave2 slave1 5ms/div
ltc2926 11 2926fa r fa and r fb . the slave output voltage varies as a function of the master signal with terms set by r ta and r tb . by selecting appropriate values of r ta and r tb , it is possible to generate any of the pro? les in figures 1 to 4. controlling the ramp-up and ramp-down behavior the operation of the ltc2926 is most easily understood by referring to the simpli? ed functional diagram in figure 6. when the on pin is low, the remote sense switch is opened and the mgate pin is pulled to ground causing the master signal to remain low. since the current through r tb1 is at its maximum when the master signal is low, the current sourced by fb1 is also at its maximum. the current forces the fb1 pin voltage above 0.8v, which pulls the sgate1 pin low and disconnects the slaves supply generator. the minimum voltage across the slave load is a function of the maximum fb1 current, the feedback divider resistors, and the load resistance (see load requirements). when the on pin rises above 1.23v, the master signal ramps up, and the slave supply tracks the master signal. the master ramp rate is set by an external capacitor driven by a 10a current source from an internal charge pump. if no external mosfet is used for the master signal, the ramp rate is set by tying the mgate and ramp pins together at one terminal of the external capacitor (see ratiometric tracking example or supply sequencing example). the mgate pin voltage will be limited to v cc + 1v (max) by the weak internal clamp on the ramp pin. the rising master signal decreases the tracking current mirrored out of the fb1 pin. the gate controller circuitry maintains 0.8v at fb1 by driving the sgate1 voltage and, via the external mosfet source-follower, the slave supply output. when the slave supply output reaches the slave supply module voltage, the fb1 pin will fall below 0.8v and the gate controller will drive the sgate1 pin above v cc to fully enhance the mosfet. after the mgate, sgate1 and sgate2 pins reach their maximum voltages, the rsgate pin is pulled up by a 10a current source from an internal charge pump, which closes the integrated remote sense switches. the integrated remote sense switch allows the slave supply generator to compensate for voltage drop across the slaves mosfet (q1). when the on pin falls below v on(th) C v on(th) , typically 1.16v, the remote sense switch opens and the mgate pin pulls down with 10a. the master signal and the slave supplies will fall at the same rate as they rose previously, following the tracking or sequencing pro? le in reverse. the on pin can be controlled by a digital i/o pin or it can be used to monitor an input supply. by connecting a resistive voltage divider from an input supply to the on pin, the supplies will ramp up only after the monitored supply reaches a preset voltage. figure 5. simpli? ed tracking cell and gate controller cell combination applicatio s i for atio wu u u r tb r ta 2926 f05 ltc2926 gate controller cell sgate 0.8v 10 a fb supply track i fb i track master ramp slave r fb r fa 10 a 0.8v v cc q ext v cc + 5v C + tracking cell C +
ltc2926 12 2926fa 0.8v 2926 f06 fb1 rampbuf track1 gnd v cc 0.8v v cc 1x d1 s1 v cc + 4.9v sgate2 10 a 10 a charge pump to rsgate pin remote sense switch 10 a 10 a charge pump sgate1 C + C + v cc + 4.9v sgate1 C + ramp + 4.9v mgate C + C + 10 a 10 a charge pump 1.23v C + on on/off mgate c mgate ramp out supply module sense r x1 out supply module master slave1 r fb1 r fa1 q0 q1 r tb1 r ta1 figure 6. simpli? ed functional block diagram optional master supply mosfet figure 7 illustrates how an optional external n-channel mosfet (device q0) can ramp up a supply that doubles as the master signal. the mosfets gate is tied to the mgate pin and its source is tied to the ramp pin. the mgate pin sources or sinks 10a to ramp the mosfets gate up or down at a rate set by the external capacitor connected to the mgate pin. the series mosfet controls any supply with an output voltage between 0v and v cc . to compensate for voltage drop across the master supply mosfet, add an optional external remote sense switch (device q3 in figure 7) connected between ramp and the sense input of the master voltage supply module. tie the gate of the external switch mosfet to the rsgate pin for automatic remote sense switching. applicatio s i for atio wu u u
ltc2926 13 2926fa figure 7. typical application with master supply r tb1 r ta1 2926 f07 ltc2926 s1 fb1 out in sense rampbuf track1 track2 gnd pgtmr v in r tb2 r ta2 fault 10k 0.1 f c pgtmr c mgate mgate 10 ? rsgate ramp r x0 v in status status/pgi on on/off 10k 3.3v module v in q0 q3 sgate2 10 ? q2 sgate1 10 ? master d1 r fb1 r fa1 s2 fb2 d2 r fb2 r fa2 fault v cc v in out in sense r x1 1.8v module v in q1 1.8v slave1 out in sense r x2 2.5v module v in 2.5v slave2 figure 8. typical application without master supply ramp buffer the rampbuf pin provides a buffered version of the ramp pin voltage that drives the resistive dividers on the track pins. when there is no external mosfet, it sources or sinks up to 3ma to drive the track resistors even though the mgate pin only supplies 10a (figure 8). the rampbuf pin also proves useful in systems with an external mosfet. if r tbn were directly connected to the mosfets source (the master output), the servo mechanism of the tracking cell could potentially drive the master output towards 0.8v when the mosfet is off. the ramp buffer prevents this by eliminating that path for current. fault input/output the fault pin allows external upstream monitoring circuits to control and to communicate with the ltc2926. the pin is driven internally by an n-channel mosfet pull-down to gnd, and by an 8.5a pull-up to v cc through a series diode. under normal conditions, the mosfet is off and the current pulls the fault pin voltage high. when an upstream monitor signal pulls fault below 0.5v, the ltc2926s internal fault latch is set, which immediately opens the remote sense switches and cuts off the master and slave supplies by pulling mgate, sgate1 and sgate2 to gnd. a fault also activates the internal mosfet pull-down on the status/pgi pin, which indicates to external downstream monitoring circuits that the supplies are no longer valid (see status output). until the fault latch is reset, the sup- plies stay disconnected and an internal pull-down keeps the fault pin low as a signal to upstream monitors. fault latch reset is initiated by bringing the on pin voltage below 0.5v, and completed when pgtmr is <0.1v. reduc- ing the v cc pin voltage below v cc(uvlo) C v cc(uvlo) , typically 2.35v, also resets the fault latch. after it is cleared, the fault latch is armed by bringing the on pin voltage above 0.6v. no faults can be latched until after the latch is armed. the fault pin is pulled up by 8.5a to v cc through a schottky diode, which allows the pin to be pulled safely above the ltc2926s supply if required. leave the fault pin unconnected if it is unused. applicatio s i for atio wu u u r tb1 r ta1 2926 f08 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr v in r tb2 r ta2 fault 10k 0.1 f c pgtmr c mgate mgate rsgate ramp v in status status/pgi on on/off 10k sgate2 10 ? q2 nc sgate1 10 ? d1 r fb1 r fa1 s2 fb2 d2 r fb2 r fa2 fault v cc v in out in sense r x1 1.8v module v in q1 1.8v slave1 out in sense r x2 2.5v module v in 2.5v slave2
ltc2926 14 2926fa status output the output aspect of the status/pgi pin allows the ltc2926 to control and communicate with external downstream circuits. the pin is driven internally by an n-channel mosfet pull-down to gnd and a 10a pull- up to an internal charge pump. the pull-down keeps the status/pgi pin low until mgate, sgate1 and sgate2 are fully enhanced, and the remote sense switches are closed. the pull-down then shuts off, and status/pgi pin rises, indicating to downstream monitors that the supplies are fully ramped up. the status/pgi pin pulls low when the mgate, sgate1, sgate2 or rsgate pin is low, either because a fault has been latched, or because the on pin is low. an internal charge pump rail at v cc + 5.5v sources the status/pgi pull-up current. an external resistor may be added to create logic level voltages, or the pin may be used to enhance the gates of external n-channel mosfet switches, if desired. power good timeout the input aspect of the status/pgi pin allows external downstream monitoring circuits to control the ltc2926 as shown in figure 9. the power good timeout circuit discon- nects the supply generators if for any reason the voltage level of the status/pgi pin is not high after the timeout period. during a ramp-up, the timeout circuit will trip if the internal pull-down on status/pgi fails to release, which indicates that supply ramping was not completed in the time allotted. if supply ramping completes, any downstream circuits that pull down the status/pgi pin after the timer duration also will trip the timeout circuit. a fault caused by a power good timeout has the same effect as a fault triggered by the fault pin: supplies are disconnected and the fault latch is set. the fault latch may be cleared as described in the fault input/output section above. the power good timer duration is con? gured by a capacitor tied between pgtmr and gnd. the pins 10a current source ramps up the capacitor voltage when the on pin is high, otherwise 4ma pulls pgtmr to gnd. the capacitor, c pgtmr , required to con? gure the power good timeout duration, t pgtmr , is determined from: c at v pgtmr pgtmr = 10 123 ? . if the power good timeout feature is not used, tie pgtmr to gnd. retry on fault the ltc2926 continuously attempts to ramp up the supplies after a fault if the fault pin is tied to the on pin. when the fault and on pins go low together, the internal fault latch is set by the falling fault pin, and the fault latch is reset by the falling on pin. a short internal delay of several microseconds guarantees triggering of fast pull-down circuits on the rsgate, mgate, sgate1 and sgate2 pins, which opens the remote sense switches and discon- nects the master and slave supplies before the fault latch is reset. if no external signal pulls down the fault pin, the internal 8.5a pull-up current or an external pull-up resistor increases the on (and fault) pin voltage above 0.6v, which arms the fault latch. a ramp-up begins when on is above 1.23v. in applications where the ltc2926 is con? gured for fault retry, some details of the retry behavior are determined by the source and duration of the fault signal. when a fault is triggered by an external pull-down signal on the fault (and on) pin, supply ramping will not restart until the low input ceases. when a power good fault is triggered by an external pull-down signal on the status/pgi pin, supply ramping restarts immediately. if the low signal persists applicatio s i for atio wu u u figure 9. external load monitor controlling ltc2926 via power good input 2926 f09 ltc2926 fb1 gnd pgtmr c pgtmr status/pgi on on/off sgate2 10 ? q2 sgate1 10 ? r fb1 r fa1 fb2 r fb2 r fa2 s1 rst v2 v1 tol s2 rst gnd 1.8v source q1 1.8v slave1 2.5v source 2.5v slave2 ltc2904 load voltage monitor (10% tolerance)
ltc2926 15 2926fa through the power good timeout period, a fault and retry will subsequently occur. to ensure a consistent power good timeout period, the ltc2926 requires the pgtmr pin voltage to fall below 0.1v for the fault latch reset to complete. the on pin needs to be held low for only 10s to initiate fault reset; it is allowed to go high while the timing capacitor on pgtmr discharges to 0.1v (see functional block diagram). when a resistive voltage divider drives the on and fault pins together, include the contribution of i fault(up) when choosing the resistor values (figure 10a). when a logic output drives both pins, up to 30k of series resistance may be added to limit the output current while the fault pull-down is active (figure 10b). automatic remote sense switching the ltc2926 provides integrated remote sense switches that solve the problem of voltage drops in the external series mosfets that control supply ramping. a switch creates a feedback path from a slave supply output to the slave supply generator sense input that allows the generator to compensate for the i ? r drop across the controlling mosfet (see, for example, figure 6). after the supply ramping is complete, but before the internal pull-down releases the status/pgi pin, the two integrated remote sense switches are closed. for applications that require more than two remote sense switches, connect the rsgate pin to the gates of additional external n-channel mosfets. an internal charge pump guarantees that rsgate will reach v cc + 5.5v, which al- lows full enhancement of logic-level mosfets with source or drain voltages up to v cc . the switches are open when supply ramping has not completed to avoid creating a power path between the supply generator and the load. when the remote sense switches are open, the supply generators sense input must be connected locally to its output through a resistor that is much larger than the remote sense switch resistance of 10 (max); a 100 resistor is adequate for most ap- plications as in figure 7. some supply modules have built-in resistors of 10 or less between their out and sense pins, which may require a lower switch resistance. choose an external n-channel mosfet with an r ds(on) that is at most 1/10 the module out-to-sense resistance, but that is still much larger than the r ds(on) of the power path mosfet. if neither external remote sense switches nor a sta- tus activation delay is required, leave the rsgate pin unconnected. applicatio s i for atio wu u u figure 10. fault retry con? gurations, (a) resistive voltage divider and (b) logic driven r onb r ona ltc2926 gnd on v cc fault v in v on qs r fault latch v cc i fault(up) r series limit i out with r series r series 30k ? i out 2926 f10 ltc2926 gnd on v cc fault v in qs r fault latch v cc i fault(up) (a) (b) v on = ? v in r ona r ona + r onb + (r ona || r onb ) ? i fault(up)
ltc2926 16 2926fa considerations when using remote sense switches consider the supply and sense path detail functional diagram and equivalent circuit in figure 11. for proper compensation of the i ? r drop across the external control mosfet q0 by the supply module, the voltage at its sense pin input must be equal to the supply voltage at the load. solving for v sense in the equivalent circuit yields: v r rr v r rr sense x xsw supply sw xsw = + ? ? ? ? ? ? ?+ + ? ? ? ? ?? ? ? v out for the best compensation, i.e., v sense v supply , choose r x >> r sw . the remote sense switch is intended to be a low-current voltage feedback path. the control mosfet (q0 in figure 11a) should carry all but a tiny fraction of the entire load current. the remote sense switch current is: ii r rr r sw load ds xswds =? ++ ? ? ? ? ? ? to minimize switch current, choose r x >> r ds . in appli- cations that use the ltc2926s integrated remote sense switches, i sw must not exceed the absolute maximum ratings for switch pin currents. it is recommended design practice to satisfy both resistance value conditions. sgate voltage at ramp start/end when the master ramp is 0v (before ramp up or after ramp down), the control mosfet ideally conducts no current. if the tracking pro? le has no delay or offset, the gate control loops may force the sgate pins either to ground or to just below the mosfet threshold voltage, depending on reference offsets, resistor mismatches and the load resistance. in both cases the slave load will be at about 0v, but if a known state of sgate is desired, include an offset in the tracking pro? le. to guarantee grounding of the sgate pins at ramp = 0v, include a positive offset, v os , based on the maximum slave supply voltage, v slave (max), and the tracking/feedback resistor tolerance. note that at the start of ramp up, the gate capacitance of the mosfet must be charged to the threshold voltage before the source begins ramping. the sgate pins do provide extra current to speed the initial charging. calculate the required v os from: v os k ? v slave (max) for 1% resistors k = 1/8, for 5% resistors k = 1/4, for 10% resistors k = 2/5. to guarantee the sgate pins sit at the mosfet threshold voltages at ramp = 0v, include a negative offset. note that when the master ramp goes to 0v, the slave supplies will remain above ground by the magnitude of the offset. calculate the required v os from: v os Ck ? v slave (max) figure 11. supply and sense path detail, (a) functional diagram and (b) equivalent circuit when remote sense switch is closed applicatio s i for atio wu u u load 2926 f11 out sense mgate rsgate (a) r x i sw supply module + v ds C q0 q3 master supply i l v out v sense (b) r x i sw r sw + v ds C r ds v supply
ltc2926 17 2926fa three-step design procedure the following three-step design procedure allows one to choose the fbn resistors, r fan and r fbn , the trackn resistors, r tan and r tbn , and the master ramp capacitor, c mgate , that give any of the tracking or sequencing pro? les shown in figures 1 to 4. a three-supply application circuit is shown in figure 12. 1. set the ramp rate of the master signal. solve for the value of c mgate , the capacitor on the mgate pin, based on the desired ramp rate (volts per second) of the master ramp signal, s m , and the mgate pull-up current i mgate , which is nominally 10a. c i s mgate mgate m = (1) if the master ramp signal is a master supply, consider the gate capacitance of the required external n-channel mosfet. if the gate capacitance is comparable to c mgate , reduce the external capacitors value to compensate for the gate capacitance of the mosfet. if the master ramp signal is not a master supply, tie the ramp pin to the mgate pin. 2. choose the feedback resistors based on the slave supply voltage and slave load. it is important that the feedback resistors are signi? cantly larger than the load resistance, especially as the slave voltage nears ground (see load requirements). first determine the effective slave load resistance, r l (not shown), at low slave voltage levels, and select the value of the top feedback resistor, r fb , to satisfy: r fb 100 ? r l (recommended), r fb 23 ? r l (required) (2) second, determine a value for the lower feedback resistor, r fa , that will ensure that the ltc2926 fully enhances the gate of the slave control mosfet at the end of ramping. select r fa based on r fb , the resistor tolerance, tol r , and the maximum slave supply voltage, v slave (max): rr tol tol v v fa fb r r slave ltc2926 18 2926fa nc r tb1 15.0k r ta1 9.53k 2926 f14 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr v in r tb2 15.0k r ta2 5.76k fault 10k c pgtmr 1 f c mgate 0.1 f mgate 0.1 f 10 ? v cc ramp v in status status/pgi on on/off rsgate 10k 3.3v v in q0 irf7413z sgate2 10 ? q2 irf7413z sgate1 10 ? 3.3v master d1 r fb1 15.0k r fa1 9.53k s2 fb2 d2 r fb2 15.0k r fa2 5.76k fault out in sense r x1 100 ? 1.8v module 3.3v q1 irf7413z 1.8v slave1 out in sense r x2 100 ? 2.5v module 3.3v 2.5v slave2 figure 14. coincident tracking example before the master ramp reaches its ? nal value; otherwise, the slave supply voltage will be held below its intended level. calculate the upper track resistor, r tb , from: rr s s tb fb m s =? ? ? ? ? ? ? (4) choose a voltage difference between the master and slave ramps, v, if offset tracking is desired. if a time delay is desired for supply sequencing, calculate an effective volt- age difference based on the master ramp rate. if neither voltage offset nor time delay is required, set v = 0v. v = a voltage difference (offset tracking), or (5a) v = s m ? t dly (supply sequencing), or (5b) v = 0v (coincident/ratiometric tracking) (5c) use the following formula to determine the lower track resistors, r ta , using the track pin voltage, v track , and the fb pin internal reference voltage, v fb(ref) , both from the electrical characteristics: r v v r v r v r ta track fb ref fb fb ref fa track tb = +? () () ++ ? v r tb (6) note that large ratios of slave ramp rate to master ramp rate, s s /s m , may result in negative values for r ta . in such cases increase the offset or delay, or reduce the slave ramp rate to realize positive values of r ta . applicatio s i for atio wu u u figure 13. coincident tracking waveforms from figure 14 circuit coincident tracking example a typical three-supply application is shown in figure 14. the master signal is 3.3v, the slave 1 supply is a 1.8v module, and the slave 2 supply is a 2.5v module. allow for 10% tolerance of the slave supply voltages. both slave supplies track coincidently with the 3.3v master supply that is controlled by an external mosfet. the ramp rate of the supplies is 100v/s. the slave supplies minimum load resistances are 150 . the external con? guration resistors 500mv/div master slave2 slave1 5ms/div 2926 f13 500mv/div 5ms/div
ltc2926 19 2926fa have 1% tolerance. the 3-step design procedure detailed above can be used to determine component values. only the slave 1 supply is considered here, as the procedure is the same for the slave 2 supply. 1. set the ramp rate of the master signal. from equation 1: c a vs f mgate == 10 100 01 . 2. choose the feedback resistors based on the slave supply voltage and slave load. r l = 150 from equation 2: r fb 100 ? 150 = 15k choose r fb = 15.0k . from equation 3: rk v v fa ltc2926 20 2926fa figure 16. ratiometric tracking example nc r tb1 24.9k r ta1 7.68k 2926 f16 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr v in r tb2 18.2k r ta2 5.36k fault 10k c pgtmr 1 f c mgate 0.1 f mgate 0.1 f v cc ramp v in status status/pgi on on/off rsgate 10k 3.3v v in sgate2 10 ? q2 irf7413z sgate1 10 ? d1 r fb1 15.0k r fa1 9.53k s2 fb2 d2 r fb2 15.0k r fa2 5.76k fault out in sense r x1 100 ? 1.8v module 3.3v q1 irf7413z 1.8v slave1 out in sense r x2 100 ? 2.5v module 3.3v 2.5v slave2 applicatio s i for atio wu u u figure 15. ratiometric tracking waveforms from figure 16 circuit 500mv/div slave2 slave1 5ms/div 2926 f15 500mv/div 5ms/div ratiometric tracking example this example converts the coincident tracking example to the ratiometric tracking pro? le shown in figure 15, using two slave supplies and a master ramp signal (not a master ramp supply). the ramp rate of the master signal remains unchanged (step 1), the minimum load resistance of the slave loads remains unchanged (step 2), and there is no delay in ratiometric tracking. only step 3 of the three-step design procedure needs to be considered. in this example, the ramp rate of the 1.8v slave supply is 60v/s, and the ramp rate of the 2.5v supply is 83.3v/s. always verify that the chosen ramp rate will allow the supplies to ramp-up completely before rampbuf reaches v cc . if the 1.8v slave supply were to ramp up at 50v/s it would only reach 1.65v because the rampbuf signal would reach its ? nal value of v cc = 3.3v before the slave supply reached 1.8v. 3. solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. from equation 4: rk vs vs k tb =? ? ? ? ? ? ? = 15 0 100 60 25 . ?? choose r tb = 24.9k . since no offset or delay is required, equation 5c applies: v = 0v from equation 6: r v v k v k v k v ta = +?+ 08 08 15 0 08 953 08 24 9 0 . . . . . . . ??? 224 9 761 . . k k ? ? = choose r ta = 7.68k .
ltc2926 21 2926fa offset tracking example converting the circuit in the coincident tracking example to the offset tracking pro? le shown in figure 17 is relatively simple. here the 1.8v slave supply ramps up 1v below the master, and the 2.5v slave supply ramps up 0.5v below the master. the ramp rate remains the same (100v/s), as do the slave supplies minimum load resistances, so there are no changes necessary to steps 1 or 2 of the three-step applicatio s i for atio wu u u figure 17. offset tracking waveforms from figure 18 circuit design procedure. only step 3 must be considered. be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. in this example, if the voltage offset on the 1.8v supply were 2v, it could ramp up only to 3.3v C 2v = 1.3v. 3. solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. from equation 4: rk vs vs k tb =? ? ? ? ? ? ? = 15 0 100 100 15 . ?? choose r tb = 15.0k . since offset is required, equation 5a applies: v = 1.0v from equation 6: r v v k v k v k ta = +?+ 08 08 15 0 08 953 08 15 0 1 . . . . . . . . ??? 00 15 0 531 v k k . . ? ? = choose r ta = 5.36k . 500mv/div master slave2 slave1 5ms/div 2926 f17 500mv/div 5ms/div figure 18. offset tracking example r tb1 15.0k r ta1 5.36k 2926 f18 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr v in r tb2 15.0k r ta2 4.64k fault 10k c pgtmr 1 f c mgate 0.1 f mgate 0.1 f 10 ? v cc ramp v in status status/pgi on on/off nc rsgate 10k 3.3v v in q0 irf7413z sgate2 10 ? q2 irf7413z sgate1 10 ? 3.3v master d1 r fb1 15.0k r fa1 9.53k s2 fb2 d2 r fb2 15.0k r fa2 5.76k fault out in sense r x1 100 ? 1.8v module 3.3v q1 irf7413z 1.8v slave1 out in sense r x2 100 ? 2.5v module 3.3v 2.5v slave2
ltc2926 22 2926fa applicatio s i for atio wu u u supply sequencing example in figure 19, the two slave supplies are sequenced using a master ramp signal. as in the ratiometric tracking example, the master signal ramps up at 100v/s, and the minimum slave loads are the same as the coincident example, so steps 1 and 2 remain the same. the 1.8v slave 1 supply ramps up at 1000v/s beginning 10ms after the master signal starts to ramp up. the 2.5v slave 2 supply ramps up at 1000v/s beginning 20ms after the master signal starts to ramp up. note that not every combination of ramp rates and delays is possible. small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. in such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. 3. solve for the tracking resistors that set the desired ramp rate and voltage offset or time delay of the slave supply. from equation 4: rk vs vs k tb =? ? ? ? ? ? ? = 15 0 100 1000 15 .. ?? choose r tb = 1.50k . since a delay is required, equation 5b applies: v = 100v/s ? 10ms = 1v from equation 6: r v v k v k v k v ta = +?+ 08 08 15 0 08 953 08 150 1 . . . . . . . ??? 1 150 296 . . k k ? ? = choose r ta = 2.94k . note that the values of r fa2 and r fb2 are larger than those of the coincident tracking example. larger feedback resis- tor values resulted in larger tracking resistor values for r ta2 and r tb2 , which limits the maximum track2 pin current to <1ma; see final sanity checks. figure 19. supply sequencing waveforms from figure 20 circuit 500mv/div slave2 slave1 5ms/div 2926 f19 500mv/div 5ms/div figure 20. supply sequencing example nc r tb1 1.50k r ta1 2.94k 2926 f20 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr v in r tb2 2.49k r ta2 1.33k fault 10k c pgtmr 1 f c mgate 0.1 f mgate 0.1 f v cc ramp v in status status/pgi on on/off rsgate 10k 3.3v v in sgate2 10 ? q2 irf7413z sgate1 10 ? d1 r fb1 15.0k r fa1 9.53k s2 fb2 d2 r fb2 24.9k r fa2 9.53k fault out in sense r x1 100 ? 1.8v module 3.3v q1 irf7413z 1.8v slave1 out in sense r x2 100 ? 2.5v module 3.3v 2.5v slave2
ltc2926 23 2926fa applicatio s i for atio wu u u slave control without mosfets the ltc2926 can control tracking and sequencing of a slave supply without a mosfet if the supply generators output voltage is set by an accessible resistive voltage divider and if its voltage reference is ground-based. track- ing currents mirrored to the fb pins are injected into the feedback nodes of the supply generators to control the output voltage. when master ramp signal has reached it maximum voltage, the fb pin current is zero, and the ltc2926 has no effect on the output voltage accuracy, transient response or stability of the generator. to control a supply generator (e.g., dc/dc converter) with a feedback reference voltage v fb(gen) of 0.75v or less, connect the fb pin of the ltc2926 to the tap point of the generators resistive divider, as shown in figure 21a. fol- low steps 1 and 3 of the three-step design procedure to set the ramp rates and tracking pro? le. use the feedback resistor values required by the supply generator for r fa and r fb in step 3. a generator with v fb(gen) >0.75v may be controlled without a mosfet if the slave voltage is large enough (see figure 22). first follow steps 1 and 3 of the three-step design procedure to set the ramp rates and tracking pro? le. use the feedback resistor values required by the supply generator in step 3. next, split resistor r fa as in figure 21b, so that rr v v and faa fa fb gen ? . () 075 r fab = r fa C r faa and tie the ltc2926s fb pin to the node in between. the new tap point allows the ltc2926s fb pin to see <0.75v at the end of ramp-up. finally, scale the track resistors to match r faa : = + ? r r rr r ta faa faa fab ta and = + ? r r rr r tb faa faa fab tb voltage regulators that force their reference voltage be- tween their output and feedback nodes do not employ a ground-based reference, and thus will not be controllable by the ltc2926 without a series mosfet. figure 21. slave supply control without a mosfet (a) generator reference v fb(gen) 0.75v and (b) generator reference v fb(gen) > 0.75v out supply generator in fb gnd v fb(gen) v in slave C + nc r tb r ta ltc2926 rampbuf track gnd sgate fb (a) r fa nc r tb r ta 2926 f21 ltc2926 rampbuf track gnd sgate fb out supply generator in fb gnd v fb(gen) v in slave (b) r fab r fb r faa C + r fb v fb(gen) (v) 0 v slave (v) 6 5 4 3 2 1 0 0.25 0.50 0.75 1.00 2926 f22 1.25 1.50 control via fb pin control via fb pin and split r fa resistor mosfet control only figure 22. regions of possible slave control without a mosfet slave supply control without a mosfet
ltc2926 24 2926fa applicatio s i for atio wu u u final sanity checks the collection of equations below is useful for identifying unrealizable solutions. as stated in step 3 of the design procedure, the slave supply must ? nish ramping before the master signal has reached its ? nal voltage. this can be veri? ed with the following equation: vv r r master track tb ta >?+ ? ? ? ? ? ? 1 here, v track = 0.8v. v master is the ? nal voltage of the master signal, either the supply voltage ramped up through the optional external mosfet or v cc when no mosfet is present. it is possible to choose resistor values that require the ltc2926 to supply more current than the electrical char- acteristics table guarantees. to avoid this condition, check that each track pins current, i trackn , does not exceed 1ma, and that the rampbuf pin current, i rampbuf , does not exceed 3ma. to con? rm that i trackn 1ma, verify that: v rr ma track ta tb || 1 check that the rampbuf pin will not be forced to sink more than 3ma when it is at 0v and will not be forced to source more than 3ma when it is at v master . v rr v rr ma track ta tb track ta tb 11 2 2 3 || || + and v rr v rr ma master ta tb master ta tb 11 2 2 3 + + + load requirements a weak resistive load can cause static and dynamic track- ing errors. the behavior of the source-follower topology of mosfet-controlled tracking relies on the loads abil- ity to support the ramp rates and tracking currents of a particular application. consider the simpli? ed slave load schematic in figure 23. figure 23. simpli? ed slave supply load load slaven 2926 f23 out supply module qn ltc2926 sgaten fbn r fb r fa r l c l when the supplies are ramped down quickly, the load must be capable of sinking enough current to support the ramp rate. for example, if there is a large output capacitance and a weak resistive load on a particular supply, that supplys falling rate will be limited by the rc time constant of the load. in figure 24, the falling 2.5v slave cannot keep up with the falling master ramp. when the supplies are near ground, the load must be capable of sinking the tracking current without creating a large offset voltage. for weak resistive loads and slave voltage levels near ground, the tracking current (at its maximum there) can be in excess of the loads current demand. having no capability for sinking current, the mosfet shuts off. all of the mirrored tracking current that ? ows through r fb also ? ows through the load resistance, r l , which creates a voltage offset between the slave and ground. in figure 24, the 1.8v supply shows an offset from ground.
ltc2926 25 2926fa applicatio s i for atio wu u u under worst-case conditions, fb pin voltages may reach the maximum clamp voltage of 2.4v. to limit the slave voltage offset to below 100mv, choose r fb 23 ? r l . add a resistor in parallel with the load to strengthen weak resistive loads as required. start-up delays often power supplies do not start up immediately when their input supplies are applied. if the ltc2926 tries to ramp up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed, which defeats the tracking circuit. make sure the on pin does not initiate ramp-up until all supply sources are available. ramp pin clamp the ramp pin is weakly clamped to the v cc pin. when mgate and ramp are tied together their pin voltages will not exceed v cc + 1v. if the ramp pin is driven by a low impedance source that can exceed v cc , include a series resistor to limit the current to <20a. use 50k per source volt above v cc . figure 24. tracking effects of weak resistive load figure 25. layout considerations 2926 f24 500mv/div master slave2 slave1 5ms/div large l = r l c l r l r fb slave load 2926 f25 out sense 100 ? kelvin-sense connections kelvin-sense connections kelvin-sense connections supply module minimize trace length minimize trace length q1 ltc2926 s1 gnd sgate1 gnd fb1 v cc d1 r fb r fa 0.1 f 10 ? layout considerations be sure to place a 0.1f bypass capacitor as near as pos- sible to the supply pin of the ltc2926. to minimize the noise on the slave supplies outputs, keep the traces connecting the fb pins of the ltc2926 and the feedback nodes of the slave supplies resistive voltage dividers as short as possible. in addition, do not route those traces next to signals with fast transitions times. to get the best compensation of the series i ? r drops of the external mosfets, make sure the supply output nodes and the supply generator sense connections use kelvin-sensing. the feedback resistive voltage divider should kelvin-sense the slave supply output node for accuracy, as well.
ltc2926 26 2926fa .337 C .344* (8.560 C 8.738) gn20 (ssop) 0204 12 3 4 5 6 7 8910 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 15 14 13 12 11 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .058 (1.473) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 20-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) package descriptio u
ltc2926 27 2926fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711) package descriptio u 4.00 0.10 (2 sides) 2.65 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.05 19 20 1 2 bottom viewexposed pad 3.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.30 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd20) qfn 0304 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 (2 sides) 3.65 0.05 (2 sides) 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline
ltc2926 28 2926fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0506 rev a ? printed in usa typical applicatio u related parts part number description comments ltc2908 precision six supply monitor four fixed (various levels) and two adjustable input thresholds ltc2920-1/ltc2920-2 single/dual power supply margining controllers single or dual, symmetric/asymmetric high and low margining ltc2921/ltc2922 power supply trackers with input monitors monitor up to five supplies, includes remote sense switches ltc2923 power supply tracking controller controls two supplies without fets, msop-10 and dfn-12 packages ltc2925 multiple power supply tracking controller with power good timeout controls three supplies without fets, includes three shutdown control pins ltc2927 single power supply tracking controller controls single supply without fets, daisy-chain for multiple supplies nc r tb1 r ta1 2926 ta02 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr r onb r ona r tb2 r ta2 c pgtmr d2 d1 v cc status status/pgi on 10k sgate2 10 ? q1 sgate1 10 ? v cc r fb1 r fa1 s2 fb2 rsgate fault r fb2 r fa2 mgate ramp 0.1 f 10k fault out in sense r x2 supply generator 2 v in q2 slave2 c mgate out in sense r x1 supply generator 1 v in slave1 nc r tb3 r ta3 ltc2926 s1 fb1 rampbuf track1 track2 gnd pgtmr r tb4 r ta4 d2 d1 status/pgi on sgate2 10 ? q3 sgate1 10 ? v cc r fb3 r fa3 s2 fb2 rsgate fault r fb4 r fa4 mgate nc ramp 0.1 f out in sense r x4 supply generator 4 v in q4 slave4 out in sense r x3 supply generator 3 v in slave3 chaining to track/sequence more supplies

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